LSCC

Business Context and Reporting Period

Company: Lattice Semiconductor Corporation
Filing Type: Form 10-K (Annual Report)
Fiscal Year Ended: January 3, 2004 (53-week year)
Business Overview: Lattice designs, develops, and markets high-performance programmable logic devices (PLDs), including Complex PLDs (CPLDs), Field Programmable Gate Arrays (FPGAs), and Low Density PLDs (SPLDs). The company operates as a fabless semiconductor entity, relying on strategic foundry partners (Seiko Epson, UMC, Chartered Semiconductor, and Fujitsu) for wafer fabrication and third-party contractors for assembly and testing.

Key Financial Metrics (Fiscal Year 2003)

Material Changes vs. Prior Period

• Revenue Decline: Revenue decreased 9% to $209.7 million, driven by weakness in CPLD and SPLD markets. FPGA revenue grew from $28 million in 2002 to $37 million in 2003.
• Margin Compression: Gross margin declined to 57% from 60% due to distributor sales allowances, lower production yields, and price erosion on new products.
• Expense Increases: R&D expenses rose to $87.1 million (41% of revenue) due to next-generation FPGA development. SG&A expenses increased to $50.8 million, partly due to professional fees associated with financial restatements.
• Debt Restructuring: The company issued $200 million in Zero Coupon Convertible Subordinated Notes due 2010 and redeemed all outstanding 4 3/4% Convertible Subordinated Notes due 2006.
• Accounting Restatement: The company restated financial results for Q1, Q2, and Q3 of 2003. This reduced 2003 revenue by approximately $10.6 million and gross margin by $8.9 million due to errors in deferred income accounting for distributor sales.

Guidance, Outlook, and Risks

• Outlook: Management noted an improvement in business conditions in Q4 2003 continuing into Q1 2004, attributed to a strengthening PLD market and recovery in the communications sector. Future growth depends on market acceptance of new FPGA products.
• Capital Expenditures: Expected to be between $15 million and $20 million for fiscal 2004.
• Strategic Investments: The company plans to invest $100 million to $200 million in Fujitsu's new 300mm wafer fab to secure advanced technology supply.
• Material Weakness in Internal Controls: The independent auditor identified a material weakness regarding the separation of duties and review of journal entries, leading to the 2003 restatement. Management is implementing remediation steps.
• Key Risks:
  • Supply Chain: Reliance on foundries in Asia (Seiko Epson, UMC, Chartered, Fujitsu) exposes the company to supply interruptions and yield issues.
  • Market Cyclicality: The semiconductor industry is highly cyclical; downturns in communications and computing markets directly impact demand.
  • Competition: Intense competition from Altera, Xilinx, and Actel regarding product features, price, and technology.
  • Intellectual Property: Risks related to patent infringement claims and the ability to protect proprietary technology.

Investor Verification Checklist

• Restatement Impact: Verify the full extent of the accounting restatement on Q1-Q3 2003 and the effectiveness of new internal controls implemented to prevent recurrence.
• FPGA Adoption: Assess the market traction of new FPGA products, which are critical for future revenue growth as CPLD/SPLD markets remain weak.
• Foundry Relationships: Confirm the status of the strategic investment in Fujitsu and the reliability of wafer supply from current partners (Seiko Epson, UMC, Chartered).
• Liquidity Position: Monitor cash burn relative to the $277.8 million cash balance and the $184 million convertible note obligation due in 2010.
• UMC Investment: Track the valuation and potential sale of the company's significant equity stake in United Microelectronics Corporation (UMC), which is subject to market volatility.