Business Context and Reporting Period
Company: Synopsys, Inc.
Filing Type: Form 10-K (Annual Report)
Period Ended: September 30, 1999
Industry: Electronic Design Automation (EDA) Software and Services
Synopsys is a leading supplier of EDA software used to design advanced integrated circuits (ICs) and system-on-a-chip ICs. The company provides logic synthesis, verification, physical design tools, and professional consulting services. The reporting period reflects a 52-week fiscal year. Financial data for 1998 and 1997 has been restated to reflect the pooling-of-interests merger with Everest Design Automation, Inc.
Key Financial Metrics
| Metric (in thousands) | Fiscal 1999 | Fiscal 1998 | Fiscal 1997 |
|---|---|---|---|
| Total Revenue | $806,098 | $717,940 | $646,956 |
| Net Income | $161,362 | $89,446 | $81,750 |
| Diluted EPS | $2.20 | $1.29 | $1.24 |
| Gross Margin | $699,334 (86.8%) | $624,173 (86.9%) | $560,071 (86.6%) |
| Operating Income | $214,395 | $90,877 | $108,432 |
| Cash & Short-Term Investments | $704,185 | $604,630 | N/A |
| Long-Term Debt | $11,642 | $13,138 | $9,191 |
| Working Capital | $627,207 | $504,759 | $336,675 |
Material Changes vs. Prior Period
- Revenue Growth: Total revenue increased 12% to $806.1 million, driven by a 17% increase in product revenue ($505.8 million) and a 5% increase in service revenue ($300.3 million). Product revenue growth was attributed to increased worldwide licensing of EDA software.
- Profitability Surge: Net income increased 80% to $161.4 million. This significant jump was primarily due to the absence of merger-related costs and in-process research and development (IPRD) charges that impacted the prior year.
- Expense Management: Sales and marketing expenses decreased 2% to $241.6 million, largely due to the divestiture of the Viewlogic PCB/Systems business and integration synergies. Research and development expenses increased 7% to $167.1 million to support new product development.
- Geographic Shift: International revenue as a percentage of total revenue declined to 34% in 1999 from 39% in 1998, driven by strong U.S. demand and economic turmoil in Asia/Pacific markets.
- Unusual Items: Fiscal 1998 included $51.0 million in merger-related costs and $33.1 million in IPRD charges. Fiscal 1999 included $21.2 million in IPRD charges related to acquisitions (Gambit, Stanza, Smartech, etc.) but no merger-related costs.
Guidance, Outlook, and Risks
Management Outlook:
- Strategy: Synopsys is expanding into physical design tools (e.g., Chip Architect, FlexRoute) to complement its logic synthesis dominance. The company aims to offer a complete "design flow" from logic to physical design.
- Expense Expectations: Management expects R&D, Sales & Marketing, and G&A expenses as a percentage of revenue to remain at or slightly below fiscal 1999 levels for fiscal 2000.
- Liquidity: Management believes current cash, investments, and lines of credit ($120 million available) are sufficient to meet working capital and capital expenditure needs for at least the next 12 months.
Risks and Contingencies:
- Competition: The EDA industry is highly competitive. Competitors like Cadence and Avant! dominate the physical design market and are integrating logic synthesis tools. Failure to develop a complete design flow could weaken Synopsys' position.
- Revenue Volatility: Revenue is subject to seasonality (Q1 is historically weakest) and large customer order timing. A significant portion of revenue comes from a small number of large customers.
- Acquisition Risks: Recent acquisitions (Gambit, Stanza, etc.) involve in-process R&D that has not yet reached technological feasibility. Failure to commercialize these technologies would result in a loss of expected economic return.
- Year 2000: The company estimates total Year 2000 readiness costs will not exceed $8.1 million. While 99% of internal remediation is complete, risks remain regarding customer and vendor compliance.
- Personnel: Intense competition for skilled EDA engineers in Silicon Valley poses a risk of significant employee turnover.
Investor Verification Checklist
- Restated Comparables: Verify that year-over-year comparisons account for the restatement of 1998 and 1997 data due to the Everest merger and the exclusion of the Viewlogic PCB/Systems business in 1999.
- Acquisition Integration: Monitor the commercialization progress of acquired in-process R&D (Gambit, Stanza, Smartech) to ensure projected revenue targets are met.
- Physical Design Adoption: Assess market acceptance of new physical design tools (Chip Architect, FlexRoute) as this is critical to closing the gap with competitors like Cadence.
- International Exposure: Track the recovery of Asian markets, as international revenue dropped to 34% of total revenue, increasing reliance on the U.S. market.
- Stock Repurchase Program: Note the authorization of a $200 million stock repurchase program in June 1999; verify the impact on share count and EPS.