Business Context and Reporting Period
Company: Synopsys, Inc.
Filing Type: Form 10-K (Annual Report)
Period Ended: September 30, 1998
Industry: Electronic Design Automation (EDA)
Headquarters: Mountain View, California
Synopsys is a leading supplier of EDA solutions, providing integrated circuit (IC) design, verification, and analysis products, as well as consulting services. The company addresses the "designer productivity gap" and "silicon performance gap" in the semiconductor industry. The fiscal year 1998 results include the consolidation of Viewlogic Systems, Inc., acquired in December 1997 via a pooling-of-interests merger. Consequently, prior year financial data has been restated to include Viewlogic.
Key Financial Metrics
Note: Specific revenue, net income, and cash flow totals for the fiscal year are incorporated by reference from the 1998 Annual Report to Stockholders and are not explicitly stated in the provided text. The following metrics are available from the filing text:
- Research & Development Expenses: $154.4 million (Fiscal 1998), compared to $146.6 million (Fiscal 1997) and $120.0 million (Fiscal 1996).
- Capitalized Software Development Costs: Approximately $2.1 million (Fiscal 1998).
- Service Revenue Mix: Service revenue represented 40% of total revenue in Fiscal 1998, up from 37% in 1997 and 34% in 1996.
- International Sales: Represented 39% of total revenue in Fiscal 1998 (down from 41% in 1997 and 42% in 1996).
- Backlog: Approximately $241.1 million as of November 1, 1998, compared to $213.9 million on November 1, 1997.
- Allowance for Doubtful Accounts: Ended at $13.21 million for Fiscal 1998.
- Employees: 2,592 total employees as of September 30, 1998 (2,040 in the U.S., 552 international).
Material Changes and Strategic Developments
- Merger with Viewlogic: The December 1997 merger with Viewlogic Systems was accounted for as a pooling-of-interests. The IC-related business was integrated, while the PCB/Systems business was sold on October 2, 1998, to a management-led group.
- Acquisition of Everest Design Automation: In November 1998, Synopsys merged with Everest Design Automation to acquire gridless high-level routing technology, strengthening its physical design tool portfolio.
- Acquisition of Systems Science, Inc. (SSI): Completed in July 1998, forming the VERA Group to automate testbench design and reduce verification time.
- Product Launches: Introduced Design Compiler 98 (13% timing improvement), Formality (formal verification), Protocol Compiler, and new FPGA tools. Phased out Viewlogic's Motive timing analysis software in favor of PrimeTime.
- Strategic Shift: Increased focus on "design flows" rather than individual point tools to compete with rivals like Cadence and Avant!.
Outlook, Risks, and Management Commentary
Management Strategy: Synopsys aims to develop a balanced portfolio addressing both designer productivity and silicon performance. The company plans to expand its physical design tools (floor-planning, placement, routing) and professional services capabilities. It continues to invest heavily in R&D to maintain technological competitiveness.
Key Risks and Contingencies:
- Competition: The EDA industry is highly competitive. Competitors (Cadence, Mentor, Avant!) are acquiring logic design and physical design tools to offer complete design flows. Cadence's acquisition of logic design products may reduce its purchases of Synopsys software.
- Technology Gaps: Synopsys currently offers a limited range of physical design tools compared to competitors and must continue to develop or acquire these to offer a complete design flow.
- Personnel: Intense competition for skilled technical and managerial personnel. Start-ups may offer more attractive stock options, leading to potential turnover.
- Forward-Looking Statements: Actual results may differ materially from projections due to risk factors discussed in the "Factors That May Affect Future Results" section of the Annual Report.
- Legal: No material legal proceedings are pending. However, there is a risk of future intellectual property infringement claims.
Investor Verification Checklist
- Restated Financials: Verify that prior year comparisons account for the Viewlogic merger (pooling-of-interests) which restates 1997 and 1996 data.
- Revenue Composition: Confirm the trend of service revenue increasing to 40% of total revenue and its impact on margins.
- Physical Design Capabilities: Assess the integration of Everest Design Automation and the timeline for a complete physical design tool flow to compete with Cadence and Avant!.
- Backlog Quality: Review the $241.1 million backlog for potential deferrals, as customers frequently reschedule ship dates.
- R&D Efficiency: Evaluate the return on the $154.4 million R&D spend, particularly regarding new product adoption (e.g., Formality, Design Compiler 98).
- Employee Retention: Monitor turnover rates given the competitive market for EDA engineers and the reliance on key technical personnel.