LSCC

Business Context and Reporting Period

Company: Lattice Semiconductor Corporation
Filing Type: Form 10-K (Annual Report)
Period Ended: December 28, 2002
Business Overview: Lattice designs, develops, and markets high-performance programmable logic devices (PLDs) and related software. The company operates in a fabless model, sourcing wafers from foundries (Seiko Epson, UMC, Chartered Semiconductor) and utilizing third-party assembly and test subcontractors. Key product segments include Complex PLDs (CPLDs), Field Programmable Gate Arrays (FPGAs), and low-density PLDs.

Key Financial Metrics (Year Ended Dec 28, 2002)

Material Changes vs. Prior Period

• Revenue Decline: Revenue decreased 22% to $229.1 million, driven by a continued downturn in the semiconductor and PLD markets, specifically in communications and computing end markets. Unit sales dropped 19% and average selling prices fell 3%.
• Acquisitions:
  • Agere FPGA: Acquired in January 2002 for $250 million cash. This entry into the FPGA market contributed 12% of 2002 revenue but resulted in a $24.2 million charge for In-Process Research and Development (IPR&D).
  • Cerdelinx: Acquired in August 2002 for stock valued at $22.8 million. Resulted in a $5.7 million IPR&D charge.
• Net Loss Expansion: The net loss widened to $175.2 million from $109.5 million. This was significantly impacted by a $118.6 million valuation allowance charge against deferred tax assets and $29.9 million in IPR&D charges related to acquisitions.
• Goodwill Accounting Change: Adoption of SFAS 142 eliminated goodwill amortization, saving approximately $8 million in quarterly expenses, though this was offset by acquisition-related intangible amortization.
• Foundry Investment Impairment: Recorded a $36.1 million unrealized loss on UMC equity investments (reflected in Other Comprehensive Income), following a $152.8 million impairment loss in 2001.

Guidance, Outlook, Risks, and Unusual Items

• Outlook: Management anticipates continued weakness in the communications and computing markets. The company expects to spend $15 million to $20 million on capital expenditures in 2003.
• Unusual Items:
  • Tax Charge: A full valuation allowance was recorded on deferred tax assets due to uncertainties regarding realization, creating a $118.6 million tax expense.
  • Debt Extinguishment: Extinguished $51.9 million of convertible notes in 2002, recognizing a $9.3 million gain. An additional $32.8 million was extinguished in Q1 2003.
• Key Risks:
  • Market Cyclicality: Heavy dependence on communications and computing sectors which are experiencing prolonged downturns and excess inventory.
  • Supply Chain: Reliance on third-party foundries (Seiko Epson, UMC, Chartered) for wafer fabrication; disruptions or yield issues could halt production.
  • Integration Risk: Challenges in integrating the Agere FPGA business and achieving expected revenue growth from new products.
  • Goodwill Impairment: Stock price trading near book value increases the risk of future goodwill impairment charges.

Investor Verification Checklist

• Deferred Tax Assets: Verify the sustainability of the full valuation allowance and the likelihood of future tax benefits given the loss position.
• Acquisition Integration: Assess the progress of the Agere FPGA integration and whether the acquired technology is generating expected revenue to offset the $24.2 million IPR&D charge.
• UMC Investment: Monitor the market value of the remaining UMC equity stake (approx. $56.3 million) and the impact of further unrealized losses on comprehensive income.
• Debt Obligations: Review the remaining $208.1 million in convertible notes due in 2006 and the company's ability to service or extinguish this debt given current cash burn.
• Backlog Reliability: Note that backlog ($37.2 million) is heavily weighted toward distributor orders which are subject to returns and price adjustments; verify if this backlog translates to recognized revenue.