QUIK

Business Context and Reporting Period

Company: QuickLogic Corporation
Filing Type: Form 10-K (Annual Report)
Period Ended: December 31, 2001
Business Overview: QuickLogic designs and markets advanced field programmable gate array (FPGA) and embedded standard product (ESP) semiconductors. The company utilizes proprietary ViaLink technology to offer flexible, high-performance logic solutions for telecommunications, data communications, and high-performance computing markets. In August 2001, the company acquired certain assets of V3 Semiconductor, Inc., to expand its ESP product portfolio.

Key Financial Metrics

Material Changes vs. Prior Period

• Revenue Decline: Revenue decreased 39.4% to $32.3 million, driven primarily by a 52% drop in FPGA sales ($23.8 million decline) due to industry-wide demand contraction. ESP sales increased 46% ($3.0 million), largely due to the V3 acquisition.
• Margin Compression: Gross margin collapsed from 60.5% in 2000 to 32.5% in 2001. This was caused by fixed manufacturing overhead allocated over lower revenue, a $3.7 million write-off of excess die inventory, and increased direct manufacturing costs.
• Operating Loss: The company swung from a net operating income of $5.8 million in 2000 to a loss of $21.3 million in 2001. Research and Development (R&D) expenses rose to $14.3 million (44.2% of revenue) due to new product introductions and the addition of R&D centers in Toronto and Bangalore.
• Non-Operating Charges: A significant $6.8 million pre-tax, non-operating loss was recorded due to the write-down of the company's investment in Tower Semiconductor Ltd.
• Liquidity: Cash reserves decreased by $41.4 million to $28.9 million. Operating cash flow turned negative at $(20.6) million, compared to positive $4.3 million in 2000.

Guidance, Outlook, and Risks

• Outlook: Management expects gross profit percentages to return to the 50-60% range as manufacturing volumes recover. The company anticipates continued investment in R&D to accelerate the introduction of the QuickMIPS family and ESP products.
• Restructuring: In October 2001, the company reduced its worldwide headcount by approximately 20% and implemented salary reductions of 10-30% for salaried employees. A restructuring charge of $619,000 was recorded.
• Strategic Investment: The company is committed to a $25 million strategic investment in Tower Semiconductor to secure wafer capacity, with $14 million paid in 2001. Future payments depend on construction milestones.
• Risks:
  • Market Volatility: The semiconductor industry is cyclical; failure to meet expectations could cause stock price declines.
  • Competition: Intense competition from Xilinx and Altera, who control over 60% of the programmable logic market.
  • Supply Chain: Reliance on third-party foundries (Cypress, TSMC, Tower) creates risks regarding capacity and yield.
  • Legal: A putative securities class action lawsuit (Turoff v. QuickLogic) was filed in October 2001 regarding IPO underwriting practices; the company intends to defend vigorously.

Investor Verification Checklist

• Inventory Valuation: Verify the adequacy of reserves for the $3.7 million excess die inventory write-off and the remaining $13.6 million inventory balance.
• Tower Semiconductor Investment: Monitor the status of the Tower fab construction and the remaining $11 million investment obligation, as well as the recoverability of the remaining $5.4 million book value.
• Revenue Recognition: Confirm the timing of revenue recognition for distributor sales, noting that 74% of sales go through distributors where revenue is deferred until resale.
• Legal Contingencies: Track the progress of the Turoff v. QuickLogic securities class action and any potential patent infringement litigation.
• Product Mix Shift: Assess the market acceptance and revenue contribution of the new ESP product line versus the declining FPGA line.