MICROCHIP TECHNOLOGY INC quarterly report, Q4 FY1996

Business Context and Reporting Period

Company: Microchip Technology Incorporated
Filing Type: Form 10-Q (Quarterly Report)
Period Ended: December 31, 1996 (Nine months ended Dec 31, 1996)
Business Overview: The Company designs and manufactures embedded control products, primarily 8-bit microcontrollers and serial/parallel EEPROM memories. Operations include wafer fabrication, assembly, and testing, with significant foreign sales (69.2% of Q4 net sales) concentrated in Asia, Europe, and Japan.

Key Financial Metrics

MetricThree Months Ended Dec 31, 1996Nine Months Ended Dec 31, 1996Nine Months Ended Dec 31, 1995
Net Sales$87.1 million$240.7 million$213.8 million
Gross Profit$43.5 million$119.9 million$110.8 million
Gross Margin50.0%49.8%51.8%
Operating Income$20.8 million$48.9 million$42.2 million
Net Income$14.8 million$34.6 million$30.0 million
Diluted EPS$0.27$0.64$0.55
Cash from Operations (9mo)$49.6 million
Cash and Equivalents (End of Period)$22.0 million
Total Debt (Current + Long-term)$44.4 million

Note: All per share data has been restated to reflect a 3-for-2 stock split effective January 6, 1997.

Material Changes vs. Prior Period

  • Revenue Growth: Net sales increased 11.5% year-over-year for the quarter and 12.6% for the nine-month period, driven by growth in 8-bit microcontrollers and EEPROM memories.
  • Profitability: Net income for the nine months increased 15.1% to $34.6 million, despite a $5.97 million restructuring charge and a $1.58 million write-off of in-process technology related to the ASiC acquisition.
  • Margin Compression: Gross margin declined to 49.8% for the nine months (from 51.8% prior year) due to reduced 5-inch wafer production and pricing pressure on non-volatile memory products.
  • Restructuring: The Company recorded a $5.97 million pre-tax restructuring charge in the nine months ended Dec 31, 1996, covering costs for idling wafer fab capacity, a two-week fab shutdown, and a 3% headcount reduction.
  • Capital Expenditures: Capital spending decreased to $60.0 million for the nine months (from $84.8 million prior year) due to delayed expansion plans, though future spending is anticipated to rise.

Guidance, Outlook, and Risks

  • Future Capital Needs: The Company anticipates spending approximately $140 million over the next twelve months to expand wafer fabrication and test capacity. Funding will come from operations, existing credit lines, and a planned public offering.
  • Public Offering: A registration statement was filed on January 16, 1997, for the sale of 1,000,000 shares (plus over-allotment). Proceeds are intended to reduce indebtedness and fund working capital.
  • Stock Repurchases: The Company repurchased 1.33 million shares for $19.5 million during the nine-month period. Treasury stock held at period end was 534,000 shares.
  • Legal and Regulatory Risks:
    • Patent Dispute: Ongoing discussions with Lucent Technologies regarding alleged patent infringement; no agreement reached, though the Company believes a license can be obtained on reasonable terms.
    • SEC Investigation: The SEC is conducting a private investigation into the Company's February 1996 disclosure regarding revenue and earnings estimates. Management does not anticipate a material adverse effect.
  • Operational Risks: Reliance on third-party contractors for assembly and test; exposure to foreign currency fluctuations; and the cyclical nature of the semiconductor industry.

Investor Verification Checklist

  • Debt Covenants: Verify continued compliance with financial ratios required by the $90 million U.S. bank syndicate line of credit.
  • Capital Expenditure Execution: Monitor the $140 million planned capital spending and its impact on cash flow and leverage.
  • Product Mix Shift: Confirm the sustainability of the shift toward higher-margin microcontrollers versus lower-margin memory products.
  • Legal Contingencies: Track the resolution of the Lucent patent dispute and the outcome of the SEC investigation.
  • Manufacturing Transition: Assess the timeline and cost implications of transitioning the Tempe fab from 6-inch to 8-inch wafers and implementing the 0.7 micron process.